1. Field of the Invention
The present invention relates to a high electron mobility transistor.
2. Description of the Related Art
Conventionally known are high electron mobility transistors having a structure in which an InGaAs channel layer and InA.iota.As electron supply layer are formed on a semi-insulating InP substrate. A cross sectional view of the structure is shown in FIG. 9, and the production steps of manufacturing a high electron mobility transistor having the structure are shown in FIGS. 10A to 10D.
The production steps will be explained in detail. First, a buffer layer 22 of non-doped InP or InA.iota.As, which lattice-matches with InP, is formed on a semi-insulating InP substrate 21, and then, on this buffer layer 22, formed are a non-doped InGaAs channel layer 23, a non-doped InA.iota.As spacer layer 24, a high impurity concentration n-type InA.iota.As electron supply layer 25, a non-doped InA.iota.As Schottky contact layer 26, and a high impurity concentration n-type InGaAs ohmic contact layer 27, in the mentioned order (FIG. 10 A). The layers 22 to 27 are formed by an organic metal chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method.
Next, ohmic electrodes 29 and 30, serving as a source and drain, respectively, are formed by vapor deposition, and high impurity concentration n-type layers 31 and 32 are formed underneath the ohmic electrodes 29 and 30, respectively, by an alloying process (FIG. 10B). After that, a resist mask 33 having an opening at a section corresponding to the gate electrode region is formed, and while monitoring source and drain currents, a section of the ohmic contact layer 27, which corresponds to the gate region, is etched to make a recess until the InA.iota.As Schottky contact layer 26 is exposed (FIG. 10C). Lastly, a Schottky gate electrode metal layer formed of a Ti/Pt/Au multilayer is deposited, and a gate electrode 28 is patterned by a lift-off process (FIG. 10D).
Such conventional HEMTs have the following problems.
First, a Schottky barrier having a sufficient height is not formed between the InA.iota.As Schottky contact layer and the gate electrode; therefore a sufficient gate break-down voltage cannot be obtained. With a Schottky contact layer formed of such a material, the Schottky barrier height can hardly be changed by use of any type of gate electrode metal.
Second, the element characteristics, especially, the gate characteristics, widely vary. This is because the etching selectivity for wet etching between the InA.iota.As Schottky contact layer 26 and InGaAs ohmic contact layer 27 is low, and the above-mentioned recess etching for exposing the InA.iota.As Schottky contact layer 26 cannot be well controlled. If occurs a wide variance of the element characteristics, high-quality integraded circuits cannot be obtained.
Third, since impurities contained in the organic metal material for A.iota., such as Si and O are mixed into the non-doped InA.iota.As layer formed by the MOCVD method while a layer being grown, the purity of the grown layer will be poor as compared to that of the non-doped InGaAs layer. As a result, the electron mobility of the secondary electron gas (2DEG) accumulated around the interface between the InGaAs channel layer and the InA.iota.As spacer layer is lowered due to dispersion of impurities contained in the spacer layer. Further, a large leak current occurs between the InA.iota.As Schottky contact layer and the gate electrode. Thus, the performance of the device is deteriorated.
Fourth, InA.iota.As layers are easily affected when brought into contact with air or moisture, and therefore the section of the InA.iota.As layer, which is exposed when forming the gate electrode, is affected, thereby deteriorating the Schottky characteristics.
The third and fourth problems are created because InA.iota.As, which lattice-matches with InP, has the composition of In.sub.0 52 A.iota..sub.0.48 As, and the composition ratio of active A.iota. of the group III elements is as large as 0.5.
There is a technique for enhancing the characteristics of the device by making the concentration of the 2DEG higher than that of an InA.iota.As/InGaAs HEMT which lattice-matches with InP. Based on this technique, the A.iota. content ratios in the n-type InA.iota.As electron supply layer and the non-doped InA.iota.As spacer layer are made larger than 0.48, the ratio while lattice-matching, so as to enlarge the discontinuity of the conducting band between the InGaAs channel layer and the hetero junction layer. However, here arises another problem, the fifth one, the crystallization of InA.iota.As will be poor as the composition ratio of A.iota. becomes larger and larger than 0.48, and the third and fourth problems will be even worse.
In the meantime, known is a high electron mobility transistor having an InGaAs channel layer and InGaP electron supply layer (for example, Published Unexamined Japanese Patent Application (PUJPA) No. 63-228763). However, the conducting band discontinuity between InGaAs and InGaP cannot be made as large as 0.52 eV which is the case of the discontinuity between InGaAs and InA.iota.As.